NVIDIA is hiring an IP Design Verification Engineer in Bengaluru to verify its crossbar (XBAR) interconnect and memory sub-system IP. You will understand the design and micro-architecture, define the verification scope, build verification infrastructure, and write test plans and tests for complex IPs and sub-systems. The work includes creating reusable bus functional models, monitors, checkers and scoreboards using coverage-driven SystemVerilog/UVM methodology, closing functional coverage, and working with architects, designers and pre- and post-silicon teams. Candidates need a B.Tech or M.Tech (or equivalent experience) and 2 or more years of verification experience on complex IPs or units, with strong Verilog, knowledge of SystemVerilog and UVM, and experience with random stimulus, functional coverage and assertion-based verification. Memory sub-system or network interconnect experience helps you stand out.