NVIDIA is hiring a Design-for-Test (DFT) Engineer in Bengaluru. You will own DFT end to end, from RTL design through gate-level scan insertion and verification to silicon bring-up. This covers JTAG, boundary scan, security mechanisms and test clocking across different test modes and multiple ATPG configurations, plus verification and bring-up of scan ATPG and other DFT features. You will also help develop and roll out DFT methods for next-generation products and work with other chip teams to build DFT features into the design. The role asks for a BSEE or MSEE (or equivalent experience) with 2+ years of experience and good knowledge of static timing analysis and related DFT flows. Occasional travel and some late-hour online meetings around critical milestones are part of the job.