Renesas is hiring a Design Verification Engineer in Bengaluru to verify complex digital IPs and subsystems in SoCs from specification to sign-off. You will help define IP-level verification strategies, test plans, coverage models and closure criteria, build reusable UVM-based verification environments, and drive functional, code, assertion and cross-coverage closure with clear metrics. You will use constrained-random and directed tests for protocol, corner-case and stress verification, apply AI/ML-assisted techniques to speed up coverage and regressions, and work with RTL, architecture, emulation and SoC verification teams. Requirements: a Bachelor’s or Master’s in Electronics Engineering with 1–2 years of design verification experience.