Qualcomm is hiring a DFT (design for test) Engineer in its ASIC engineering group in Bengaluru. You will carry out RTL and gate-level simulation (GLS) verification at SoC level, bring up C-based test cases, debug GLS/SDF issues, and verify JTAG and boundary-scan architecture on ARM-based SoCs, analysing waveform dumps to find problems. Required skills include Verilog/SystemVerilog, basic UVM concepts, and scripting in Python, Perl or similar. Minimum qualification is a bachelor's degree in Computer Science, Electrical/Electronics Engineering or a related field with 2 or more years of hardware engineering experience, or a master's degree with relevant experience. Good communication skills are expected.