Qualcomm India is hiring a Physical Design Engineer in Chennai for subsystem implementation. You will handle floor-planning, place and route, clock tree synthesis, formal verification, physical verification (DRC/LVS), power delivery network, timing closure and power optimisation for PPA-critical cores. The role needs knowledge of timing convergence for high-frequency, data-path-heavy cores, advanced STA concepts and clocking architecture, and block-level PnR convergence using Synopsys ICC2 or Cadence Innovus with timing sign-off in PrimeTime SI or Tempus at advanced nodes. You will work closely with design, DFT and PnR teams. Requirements: a degree in electronics, electrical, computer science or a related field, 3–6 years of physical design experience, and Tcl/Perl scripting.