Arm is hiring a physical design engineer in Bengaluru with 1-2 years of ASIC physical design experience. With mentoring from senior engineers, you will run RTL synthesis, floorplanning, placement, clock tree synthesis, routing and GDSII generation, and work to improve power, performance and area. You will do static timing analysis in Synopsys PrimeTime, fix setup and hold violations, review constraints and tool reports, and help with physical verification sign-off including DRC, LVS, signal integrity and EM/IR. You will also write Python and Tcl scripts to automate tasks and analyze reports, using approved AI tools while checking their output.